1. Field of the Invention
The present invention relates to a multilayered semiconductor wafer comprising a handle wafer and a silicon carbide donor layer and to a process for manufacturing it.
2. Description of the Related Art
Gallium nitride (GaN) is often used as an active layer in semiconductor devices due to its high direct bandgap, high electron saturation velocity and high voltage blocking capability. The direct bandgap is well suited for the manufacture of green and blue LEDs and laser diodes. Crystals of gallium aluminum nitride (GaAlN) and gallium indium nitride (GaInN) may also be used for these applications, GaAlN has a larger bandgap and GaInN has a smaller bandgap. Nitride based devices are also used in microwave devices, high power devices and HEMTs.
GaN crystals are, however, difficult to grow and as yet no commercial crystal growth process is available for production of pure crystal ingots. GaN wafers are normally produced by growth of GaN on suitable substrates with subsequent removal of the substrate. These ‘quasi-bulk’ GaN wafers exhibit a high defect density and are relatively expensive to grow. In many device applications a thin layer of GaN is grown on a suitable substrate.
Silicon carbide (SiC) substrates are often used as substrates for the growth of GaN films and wafers. While these substrates offer acceptable lattice constant matching and good electrical and thermal properties for GaN growth and device features they are limited to small diameters of less than 100 mm. Monocrystalline SiC wafers are much more expensive than silicon wafers. Furthermore, bulk SiC wafers have defects such as micropipes and different polytype inclusions, the defects being generated during crystal growth.
An alternative approach is to use bulk silicon wafers for the epitaxial growth of GaN layers, either directly or via an intermediate epitaxial SiC layer. While large diameter silicon wafers are readily available, the growth of GaN films on buffer layers results in a high dislocation density which limits the use of such materials. Furthermore, cracking of the GaN film can result due to the extreme tensile stress induced by the silicon wafer on the GaN layer. The stress is a result of the different thermal expansion co-efficient of the silicon wafer and the GaN layer. If the stress is too large the wafer may even break during the epitaxial process. In addition, epitaxial growth of SiC has the disadvantage of generating many defects, particularly twins and hillocks.
It is also known to use silicon wafers as substrates for ion-beam synthesis of SiC (WO03/034484A2). In this approach, silicon wafers are implanted with carbon ions and annealed at high temperatures to produce a buried layer of SixCy below the silicon surface. The buried ion-beam synthesized SiC (IBS-SiC) layer has varying degrees of stoichiometry (x, y) and varying degrees of crystallinity without clearly defined borders to the top silicon layer and the bottom portion of the silicon substrate. The buried layer has no free surface and contains many SiC nano inclusions of different orientations, lattice defects, monocrystalline SiC regions, amorphous inclusions and end-of-range implantation damage. Under suitable implantation and annealing conditions a monocrystalline SiC region forms at a depth approximately corresponding to the mean depth of the implanted carbon ions. If the top silicon layer is removed GaN can be grown on the IBS-SiC layer. However, there is still the problem of cracking during GaN deposition due to the different thermal expansion coefficients of silicon and GaN.
The problem of cracking or wafer breakage during the epitaxial growth of the GaN layer can be solved by transferring a thin monocrystalline SiC layer to a base or handle wafer having a matching coefficient of thermal expansion, e.g. consisting of polycrystalline SiC. U.S. Pat. No. 6,328,796 discloses a method wherein a superficial 3c-SiC layer is produced by carbonizing the surface of a silicon donor wafer, bonding the SiC layer of the silicon donor wafer to a base wafer consisting of polycrystalline SiC and removing the rest of the silicon donor wafer in order to expose the SiC layer.
Carbonization of silicon substrates generates a large number of dislocations, stacking faults, voids and planar defects such as anti-phase boundaries (APBs). (Mendez et al., Materials Science Forum, Vols. 483-485 (2005), pp. 189-192) The large defect generation associated with carbonization is partially due to the large lattice mismatch between silicon and SiC (20%) and due to the coalescence of SiC islands which nucleate independently of each other with different phase and stacking orders, resulting in a high density of planar defects. (Zetterling et al., Process technology for SiC devices, EMIS Processing Series 2, ISBN 0852969988, Chapter 2, pp. 39-40) Furthermore, the C:Si ratio in the precursor gas needs to be tightly controlled during the carbonization process and the following SiC epitaxial growth in order to avoid additional defects. Epitaxial growth of SiC on the carbonized layer can reduce some of the crystal failures in the early growth phase due to self annihilation of some anti-phase boundaries, however, SiC growth is relatively slow (approximately 0.5-8 μm/hr) and the defect reduction is not very effective. Epitaxial growth will also roughen the surface due to step-like growth and nucleated defects which do not self-annihilate will continue to grow in the epitaxial process, and indeed some epitaxial related defects will in addition be nucleated and grow, for example stacking faults and growth hillocks. Furthermore, protrusions and macro-steps are an issue. (Takashi et al., Materials Science Forum, Vols. 389-393, (2002) pp. 323-326) The defect problems associated with a carbonization and a subsequent epitaxy step can be somewhat reduced with off-orientated crystals but the fundamental problems associated with SiC island coalescence and resulting twins and hillock growth remain. A further drawback of carbonization based epitaxial SiC growth on silicon is the generation of voids at the carbonized SiC/Si interface.
Finally, it has been discovered that if a GaN layer is deposited on the SiC layer and LEDs are fabricated on the GaN layer the efficiency of the LEDs is relatively low.